1. Field of the Invention
This disclosure generally relates to the design of a semiconductor chip package. More specifically, this disclosure relates to a chip package in which a set of memory structures that are stacked upon a host structure in the chip package provide a configurable-width memory channel.
2. Related Art
In many conventional computer systems, multiple DRAM devices are arranged in parallel to provide a fixed-width data interface with a memory controller. Because limited pin and routing resources in a memory module prevent individual addressing of each memory chip, memory devices within a given rank are typically accessed in lockstep using an address provided on a shared bus. In such designs, the memory controller reads and writes data in blocks of a prescribed data word, regardless of the actual number of bytes requested by the processor.
Unfortunately, such designs can lead to inefficient memory accesses. For example, consider an access for a commodity DRAM module that supports a 64-bit wide data bus. If a processor requests and uses only a single byte (e.g., eight bits) of data at random, the memory access is inefficient, because only one out of every eight bytes of data transferred is useful.
Hence, what is needed are structures and techniques for accessing memory systems without the above-described problems of existing techniques.